Shallow trench isolation (STI) has become a common and important isolation technology in an IC device. One of the purposes of STI is to prevent carriers, such as electrons or electron-holes, from drifting between two adjacent device elements through a semiconductor substrate to cause a leakage current.
A conventional STI process flow may include pad oxide layer and nitride-containing layer deposition on a substrate, active area masking, nitride-containing/oxide etching, silicon substrate trench etching, isolation oxide filling, chemical mechanical polishing, and nitride-containing layer and pad oxide layer removal.
In the conventional method, the predetermined target height of isolation oxide above the pad oxide layer cannot be well controlled. In some products, the electrical performance varies with the predetermined target height of isolation oxide. This lack of control also produces several problems, and one problem is divot formation (i.e. oxide recess) along an STI edge. Divot formation reduces device yield. The divot at the edge of the STI may be formed by having the pad oxide layer removed in a wet dip process.